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chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.
https://chipsalliance.github.io/sv-tests-results/
ISC License
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build(deps): bump third_party/cores/ibex from `b4ae5bb` to `84232a5` #6448

Open dependabot[bot] opened 8 hours ago

dependabot[bot] commented 8 hours ago

Bumps third_party/cores/ibex from b4ae5bb to 84232a5.

Commits
  • 84232a5 [rtl] Fix zero value in FPGA RF
  • f0f6bfd Block diagram: make feature text readable
  • 496e06f Block diagram: fixes and improved looks
  • fb49826 [dv] Cleanup some code in the compile_tb.py module
  • 8e77bb3 [dv] Tweak ISS linker arg construction for Xcelium
  • f92d599 [pmp] Use top-level straps for PMP reset values
  • 4ed20f4 Update more documentation links
  • 6a33f69 Update verification_stages.rst OT links
  • 2617c43 [rtl] Fix wrong address in latch RF
  • 53888bc [rtl] fix a typo.
  • Additional commits viewable in compare view


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