Formal equiv diff asicworld_code_tidbits_fsm_using_always.v

[alaindargelas]

Test yosys/tests/asicworld/code_tidbits_fsm_using_always.v

The plugin generates parameters that are 32 bit wide where they should be 3 bits wide.

[robertszczepanski]

Fixed by https://github.com/chipsalliance/yosys-f4pga-plugins/pull/402.