unique / priority not properly supported with both case and if constructs

[astrollo]

The following codes use unique (or priority) in case and in if constructs. systemverilog plugin results in an error after proc command. (Yosys 0.26+53)

Listing 1. The code is sinthesized correctly with yosys without systemverilog plugin. systemverilog plugin gives the following error, after proc: _2.8. Executing PROC_DLATCH pass (convert process syncs to latches). ERROR: Latch inferred for signal \test_unique.\y from always_comb process \test_unique.$proc$/home/user/libro/cap2/unique/testunique.sv:5$1.

module test_unique (input logic a,b, c,
  input logic [2:0] sel, output logic y);

always_comb
priority case (sel) // same error with unique 
 3'b001: y = a;
 3'b010: y = b;
 3'b100: y = c;
endcase

endmodule 

Listing 2. yosys without systemverilog plugin synthesizes a latch, while other tools like vivado infer only muxes. systemverilog plugin gives the following error after proc: _2.8. Executing PROC_DLATCH pass (convert process syncs to latches). ERROR: Latch inferred for signal \test_unique2.\y from always_comb process \test_unique2.$proc$/home/user/libro/cap2/unique/testunique2.sv:5$1.

module test_unique2 (input logic a,b, c,
input logic [2:0] sel,
output logic y);

always_comb
priority if (sel==3'b001) // same error with unique 
 y = a;
else if (sel==3'b010)
y = b;
else if (sel==3'b100)
y = c;

endmodule  

[astrollo]

I correct myself. In Listing 2 yosys without systemverilog plugin gives a syntax error: test_unique2.sv:6: ERROR: syntax error, unexpected TOK_IF, expecting TOK_CASE or TOK_CASEX or TOK_CASEZ