Open mole99 opened 11 months ago
@mole99 , the plugin does not support SystemVerilog interfaces. Surelog (the parser) does. But a critical piece is missing here.
Yosys obviously does not support them either. The plugin should transform them into modules/structs. Another solution would be to perform that transformation on the UHDM data model.
I see, thanks for the clarification! Yes, Yosys does not support them, that's why it would be great if synlig does one day :D
First of all, thank you all for your great work!
I tried to process a simple interface:
In the stage
Generating RTLIL representation for module
\bus_master'.` I get the warning:Warning: Identifier
\bus.out' is implicitly declared.`The output that is written by Yosys is not correct,
bus
isinout
and there is no output forbus.out
.