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chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
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Build(deps): Bump third_party/OpenROAD-flow-scripts from `62325bf` to `038f078` #2375

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/OpenROAD-flow-scripts from 62325bf to 038f078.

Commits
  • 038f078 Merge pull request #1861 from The-OpenROAD-Project-staging/tt_rsz_swap-metrics
  • 248e9a4 Update metrics for the reinstating of the new rsz swap
  • 48ae6c6 Merge pull request #1859 from The-OpenROAD-Project-staging/fix-cells.v
  • d0ef7dc Fix bug in module DFF_X2 in cells.v (ng45)
  • 5d11692 Merge pull request #1858 from AcKoucher/asap7-riscv32i-metrics-update
  • d0bc999 Merge pull request #1857 from Pinata-Consulting/cts-logging-cleanup
  • f6e1cdd update asap7/riscv32i metrics for mpl2 update
  • d5fc7c5 cts: more consistent handling of parameters and logging for repair_timing
  • 9adb3d4 Merge pull request #1853 from Pinata-Consulting/yosys-indigestibles
  • 71ff037 synthesis: get rid of indigestibles
  • Additional commits viewable in compare view


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github-actions[bot] commented 3 months ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..dependabot/submodules/third_party/OpenROAD-flow-scripts-038f078

dependabot[bot] commented 3 months ago

Superseded by #2379.