chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
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ERROR: Assert `size >= 1' failed in /root/synlig/synlig/frontends/systemverilog/uhdm_ast.cc:751. #2377

Open yosyssyn opened 3 months ago

yosyssyn commented 3 months ago

image I am using the following commands to load the files:

Yosys 0.33 version plugin -i systemverilog read_systemverilog -defer file_name1.sv .read_systemverilog -defer file_name2.sv read_systemverilog -defer file_name3.sv read_systemverilog -defer top.sv

read_systemverilog -link when I am linking with above command, I am getting the ERROR: Assert `size >= 1' failed in /root/synlig/synlig/frontends/systemverilog/uhdm_ast.cc:751.

alaindargelas commented 3 months ago

All the warnings above the error are of great concern. Please verify your design setup (Parameters).

yosyssyn commented 3 months ago

hi Thank you alaindargelas, I am trying to reevaluate the parameters from top file but the following error is coming image

alaindargelas commented 3 months ago

Use read_systemverilog -P<name>=<value> .... rest of the command line

yosyssyn commented 2 months ago

All the warnings above the error are of great concern. Please verify your design setup (Parameters).

The warning we are seeing is coming from one submodule where we just initialize the parameter later in top module we are assigning everything proper. In previous project I followed the same but did not see any such issues