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chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
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Build(deps): Bump third_party/OpenROAD-flow-scripts from `62325bf` to `2f1417b` #2409

Closed dependabot[bot] closed 2 months ago

dependabot[bot] commented 2 months ago

Bumps third_party/OpenROAD-flow-scripts from 62325bf to 2f1417b.

Commits
  • 2f1417b Merge pull request #1907 from The-OpenROAD-Project/update-openroad
  • fa65097 Merge pull request #1929 from Pinata-Consulting/makefile-improved-logging
  • f9c77f3 Merge pull request #1931 from Pinata-Consulting/makefile-skip-targets-are-moot
  • de74485 makefile: skip_ targets are moot with introduction of ABSTRACT_SOURCE
  • bac78f2 [BOT] Update OpenROAD submodule
  • 5078bbc makefile: improve logging, add stage label for Running line
  • 9d69b97 makefile: improve logging, include name of stage as well as which script is r...
  • 7585802 fix PR merge mistake
  • 16438b1 Mock array element latency (#1925)
  • d7d9288 Merge pull request #1924 from eder-matheus/disable_ant_check
  • Additional commits viewable in compare view


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dependabot[bot] commented 2 months ago

Superseded by #2413.