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chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
144 stars 20 forks source link

Build(deps): Bump third_party/yosys from `ea7818d` to `7bb2746` #2411

Closed dependabot[bot] closed 2 months ago

dependabot[bot] commented 2 months ago

Bumps third_party/yosys from ea7818d to 7bb2746.

Commits
  • 7bb2746 Merge pull request #4334 from YosysHQ/docs_tidy
  • 73d0215 Docs: Rename source/temp to source/generated
  • 953f5bb Docs: Remove end-before tag for yosys-abc
  • b827b98 Merge pull request #4265 from povik/iattr_help
  • 4a8cdfa Merge pull request #4169 from povik/clean-opt_clean-step2
  • ed46453 Bump version
  • b302428 Docs: Force read_verilog to avoid verific header
  • 1d7b7dd Docs: Skip footer in logs
  • d4b6042 Makefile: Separate docs/usage stderr and stdout
  • 1c09862 Merge pull request #4329 from YosysHQ/mmicko/codeowners_change
  • Additional commits viewable in compare view


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dependabot[bot] commented 2 months ago

Superseded by #2415.