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chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
159 stars 21 forks source link

Build(deps): Bump third_party/OpenROAD-flow-scripts from `62325bf` to `5ef5a3e` #2422

Closed dependabot[bot] closed 5 months ago

dependabot[bot] commented 5 months ago

Bumps third_party/OpenROAD-flow-scripts from 62325bf to 5ef5a3e.

Commits
  • 5ef5a3e Merge pull request #1943 from Pinata-Consulting/makefile-elapsed-include-memory
  • a006172 Merge pull request #1926 from The-OpenROAD-Project-staging/secure-flow-abc9
  • b91499d rebased 6 designs
  • f88ee90 Merge remote-tracking branch 'origin/master' into secure-flow-abc9
  • 1c47249 Merge pull request #1945 from hpretl/sg13g2-changefill
  • e3ae06e Merge pull request #1942 from urish/patch-1
  • 4be151b Use decoupling cells as fill cells
  • 40f7ce7 rebased 16 nm aes
  • 4eb811a makefile: print out maximum memory usage in elapsed
  • afccf3f makefile: elapsed time python code fewer red lines in editor
  • Additional commits viewable in compare view


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github-actions[bot] commented 5 months ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..dependabot/submodules/third_party/OpenROAD-flow-scripts-5ef5a3e

dependabot[bot] commented 5 months ago

Superseded by #2423.