Encountered unhandled typespec in process_typespec_member: '' of type 'array_typespec'

This looks relevant to #768 and #689, yet is caused by different language constructs.

Version

Latest release (2024-03-13-d844d8d) with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)

Reproduction Steps

SystemVerilog code top.sv:

module top;
  typedef bit   [7:0] foo_t;

  typedef struct {
    foo_t f [7];
  } bar_t;

  typedef bar_t foobar_t [2];
endmodule

Command:

yosys -p "plugin -i systemverilog; read_systemverilog top.sv"

Output:


 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)

-- Running command `plugin -i systemverilog; read_systemverilog top.sv' --

1. Executing Verilog with UHDM frontend.
[INF:CM0023] Creating log file "/tmp/slpp_all/surelog.log".
[INF:CP0300] Compilation...
[INF:CP0303] /tmp/top.sv:1:1: Compile module "work@top".
[INF:CP0302] Compile class "work@mailbox".
[INF:CP0302] Compile class "work@process".
[INF:CP0302] Compile class "work@semaphore".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] /tmp/top.sv:1:1: Top level module "work@top".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0511] Nb leaf instances: 1.
[INF:UH0706] Creating UHDM Model...
[INF:UH0707] Elaborating UHDM...
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 5
ERROR: :0: Encountered unhandled typespec in process_typespec_member: '' of type 'array_typespec'

chipsalliance / synlig

Encountered unhandled typespec in process_typespec_member: '' of type 'array_typespec' #2424

Version

Reproduction Steps