"output int" (signed) in SV is translated into "output" (unsigned) in V

[YikeZhou]

Version

Latest release (2024-03-13-d844d8d) with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)

Reproduction Steps

SystemVerilog code top.sv:

module top(output int o);
   typedef struct packed {
      logic [9:0] min_v;
   } filter_ctl_t;

   filter_ctl_t [1:0][2:0] a;
   assign a[0][0].min_v = '1;
   assign o = int'(a[0][0].min_v);
endmodule

Command:

yosys -p "plugin -i systemverilog; read_systemverilog top.sv; write_verilog -noattr"

Got the following Verilog:

/* Generated by Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os) */

module top(o);
  wire [59:0] a;
  output [31:0] o;
  wire [31:0] o;
  assign a[9:0] = 10'h3ff;
  assign o = { 22'h000000, a[9:0] };
endmodule

Expected Behavior

The output port o is declared as int in SystemVerilog. Therefore, I was expecting something like:

output signed [31:0] o;