Assert `struct_ranges.size() <= (wire_node->multirange_dimensions.size() / 2)` failed

Version

Latest release (2024-03-13-d844d8d) with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)

Reproduction Steps

SystemVerilog code ucsbece154b_victim_cache.sv: (Origin: https://github.com/sifferman/labs-with-cva6/blob/main/labs/caching/part2/starter/ucsbece154b_victim_cache.sv)

module ucsbece154b_victim_cache(
    input   logic [7:0]  raddr_i
);

localparam OFFSET_WIDTH = 1;
localparam TAG_SIZE = 1;

logic [TAG_SIZE-1:0] rtag;
assign rtag = raddr_i[OFFSET_WIDTH +: TAG_SIZE];

integer i;

typedef logic [1:0] way_index_t;

struct packed {
    logic [TAG_SIZE-1:0] tag;
    way_index_t lru;
    way_index_t mru;
    logic valid;
} dll_d[4], dll_q[4];

way_index_t lru_d, lru_q, mru_d, mru_q;
way_index_t read_index;
always_comb begin
    read_index = 'x;
    lru_d = lru_q;
    mru_d = mru_q;
    dll_d = dll_q;

    for (i = 0; i < 4; i++) begin
        if (dll_d[i].valid && (rtag==dll_d[i].tag)) begin
            read_index = way_index_t'(i);
            break;
        end
    end
end
endmodule

Command:

yosys -p "plugin -i systemverilog; read_systemverilog ucsbece154b_victim_cache.sv"

Output:

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)

-- Running command `plugin -i systemverilog; read_systemverilog ucsbece154b_victim_cache.sv' --

1. Executing Verilog with UHDM frontend.
[INF:CM0023] Creating log file "/tmp/slpp_all/surelog.log".
[INF:CP0300] Compilation...
[INF:CP0303] /tmp/ucsbece154b_victim_cache.sv:1:1: Compile module "work@ucsbece154b_victim_cache".
[INF:CP0302] Compile class "work@mailbox".
[INF:CP0302] Compile class "work@process".
[INF:CP0302] Compile class "work@semaphore".
[INF:EL0526] Design Elaboration...
[NTE:EL0503] /tmp/ucsbece154b_victim_cache.sv:1:1: Top level module "work@ucsbece154b_victim_cache".
[NTE:EL0508] Nb Top level modules: 1.
[NTE:EL0509] Max instance depth: 1.
[NTE:EL0510] Nb instances: 1.
[NTE:EL0511] Nb leaf instances: 0.
[INF:UH0706] Creating UHDM Model...
[INF:UH0707] Elaborating UHDM...
[  FATAL] : 0
[ SYNTAX] : 0
[  ERROR] : 0
[WARNING] : 0
[   NOTE] : 5
Warning: /tmp/ucsbece154b_victim_cache.sv:30: Post-incrementation operations are handled as pre-incrementation.
ERROR: Assert `struct_ranges.size() <= (wire_node->multirange_dimensions.size() / 2)' failed in /root/synlig/synlig/frontends/systemverilog/uhdm_ast.cc:1012.

I noticed the warning before the error. Though, I was afraid not to be able to find the connections between them.

As far as I tried, the failed assertion below was caused by dll_d[i].valid && (rtag==dll_d[i].tag) in the conditional statement. https://github.com/chipsalliance/synlig/blob/d844d8d88520e07fa8c6e400ce5a117f7afee700/frontends/systemverilog/uhdm_ast.cc#L1012

Since the commercial tools available on https://www.edaplayground.com/ didn't complain about the code, I guess there might be a bug here.

chipsalliance / synlig

Assert `struct_ranges.size() <= (wire_node->multirange_dimensions.size() / 2)` failed #2427

Version

Reproduction Steps