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chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
159 stars 21 forks source link

Build(deps): Bump third_party/sv2v from `e9c01d2` to `fdfa597` #2438

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/sv2v from e9c01d2 to fdfa597.

Commits
  • fdfa597 upgrade system severity task AST representation
  • 70ec448 remove iverilog workaround from typeof_scope.sv
  • 429dc5a use --pvp-bounds upper for future releases
  • 9ba03f9 release v0.0.12
  • 7cf4944 prepare for the next release
  • 4dc672b bump license year
  • a4928a8 swap order of regexes in notice.sh
  • 988f76b broaden compiler support
  • bc1329a populate version in CI
  • a80919b filter crlf in notice
  • Additional commits viewable in compare view


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github-actions[bot] commented 3 months ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..dependabot/submodules/third_party/sv2v-fdfa597

dependabot[bot] commented 3 months ago

Superseded by #2444.