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chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
159 stars 21 forks source link

Build(deps): Bump third_party/sv2v from `e9c01d2` to `52197df` #2454

Closed dependabot[bot] closed 3 months ago

dependabot[bot] commented 3 months ago

Bumps third_party/sv2v from e9c01d2 to 52197df.

Commits
  • 52197df add bugpoint mode
  • 73a9cc6 logic conversion handles tf output ports
  • 1c90277 parser support for not, strong, weak, nexttime, and s_nexttime
  • 636130f add weekly coverage build
  • d3dbaf0 handle resetall when creating implicit nets
  • 6eda946 handle directives when writing to a directory
  • fdfa597 upgrade system severity task AST representation
  • 70ec448 remove iverilog workaround from typeof_scope.sv
  • 429dc5a use --pvp-bounds upper for future releases
  • 9ba03f9 release v0.0.12
  • Additional commits viewable in compare view


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dependabot[bot] commented 3 months ago

Superseded by #2456.