Synlig has a problem with nested if else

[Kreijstal]

Given this code.

  95   │   always_ff @(posedge clk_i, negedge rst_ni) begin
  96   │     if (~rst_ni) begin
  97   │       isdifferent <= '0;
  98   │       middleVariable <= '0;
  99   │     end else begin
 100   │       if (middleVariable != regC) begin
 101   │         isdifferent <= 1'b1;
 102   │         middleVariable <= regC;
 103   │       end // if(middleVariable)
 104   │          else if (isdifferent==1'b1&&(regB!=cnt||shift!=5'd7))
 105   │          begin
 106   │         isdifferent <= 1'b1;
 107   │       end else begin
 108   │         isdifferent <= 0'b0;
 109   │       end
 110   │     end  // if (~rst_ni) else
 111   │   end

with error message

[SNT:PA0207] /home/kreijstal/git/riscvxu/src/rtl/student/student_rlight.sv:99:8: Syntax error: rule conditional_statement failed predicate: _input->LA(1) != ELSE?,
    end else begin
        ^-- /home/kreijstal/git/riscvxu/src/rtl/student/slpp_all/lib/work/student_rlight.sv:99:8:.
[SNT:PA0207] /home/kreijstal/git/riscvxu/src/rtl/student/student_rlight.sv:107:10: Syntax error: rule conditional_statement failed predicate: _input->LA(1) != ELSE?,
      end else begin
          ^-- /home/kreijstal/git/riscvxu/src/rtl/student/slpp_all/lib/work/student_rlight.sv:107:10:.
[SNT:PA0207] /home/kreijstal/git/riscvxu/src/rtl/student/student_rlight.sv:108:24: Syntax error: extraneous input ''b0' expecting ';',
        isdifferent <= 0'b0;
                        ^-- /home/kreijstal/git/riscvxu/src/rtl/student/slpp_all/lib/work/student_rlight.sv:108:24:.

synlig does not like this type of structure.

Complete error

``` kreijstal@kreijstalnuc:~/git/riscvxu/src/rtl/student$ ~/git/synlig/out/current/bin/yosys -p "plugin -i systemverilog" -p "read_systemverilog adder.sv biquad_equation.sv biquad_filter.sv clock_generator.sv coefficient_decision.sv filter_coefficients_pkg.sv i2s_biquad_adapter.sv i2s_receiver.sv i2s_top.sv i2s_transmitter.sv multiplier.sv sine_wave_gen.sv student_decider.sv student_dma.sv student_i2c.sv student_irq_ctrl.sv student_rlight.sv student_tlul_mux.sv student.sv" -p "hierarchy -check -top student" -p "proc" -p "write_json student.json" /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Xenia Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.38+4 (git sha1 ac0fb2e30, c++ 14.1.1 -fPIC -Os) -- Running command `plugin -i systemverilog' -- -- Running command `read_systemverilog adder.sv biquad_equation.sv biquad_filter.sv clock_generator.sv coefficient_decision.sv filter_coefficients_pkg.sv i2s_biquad_adapter.sv i2s_receiver.sv i2s_top.sv i2s_transmitter.sv multiplier.sv sine_wave_gen.sv student_decider.sv student_dma.sv student_i2c.sv student_irq_ctrl.sv student_rlight.sv student_tlul_mux.sv student.sv' -- 1. Executing Verilog with UHDM frontend. [INF:CM0023] Creating log file "/home/kreijstal/git/riscvxu/src/rtl/student/slpp_all/surelog.log". [NTE:PP0128] /home/kreijstal/git/riscvxu/src/rtl/student/adder.sv:57:66: Non ASCII character detected, replaced by space. [NTE:PP0128] /home/kreijstal/git/riscvxu/src/rtl/student/multiplier.sv:49:59: Non ASCII character detected, replaced by space. [SNT:PA0207] /home/kreijstal/git/riscvxu/src/rtl/student/student_rlight.sv:99:8: Syntax error: rule conditional_statement failed predicate: _input->LA(1) != ELSE?, end else begin ^-- /home/kreijstal/git/riscvxu/src/rtl/student/slpp_all/lib/work/student_rlight.sv:99:8:. [SNT:PA0207] /home/kreijstal/git/riscvxu/src/rtl/student/student_rlight.sv:107:10: Syntax error: rule conditional_statement failed predicate: _input->LA(1) != ELSE?, end else begin ^-- /home/kreijstal/git/riscvxu/src/rtl/student/slpp_all/lib/work/student_rlight.sv:107:10:. [SNT:PA0207] /home/kreijstal/git/riscvxu/src/rtl/student/student_rlight.sv:108:24: Syntax error: extraneous input ''b0' expecting ';', isdifferent <= 0'b0; ^-- /home/kreijstal/git/riscvxu/src/rtl/student/slpp_all/lib/work/student_rlight.sv:108:24:. [ FATAL] : 0 [ SYNTAX] : 3 [ ERROR] : 0 [WARNING] : 0 [ NOTE] : 2 ERROR: Error when parsing design. Aborting! ```

[Kreijstal]

is this a UHDM only bug, and should be filed there?

[alaindargelas]

Your best bet is to rewrite this code in a less convoluted way. But your can check if Vivado supports the code. Provide a fully compiling testcase with all declarations, not just a code snippet and file the issue under Surelog.

[Kreijstal]

Vivado does simulate synthetise and tested in hardware in fpga.