Fail CI on every result difference

chipsalliance / synlig

SystemVerilog synthesis tool

Apache License 2.0

169 stars 22 forks source link

Fail CI on every result difference #2553

Closed kamilrakoczy closed 2 months ago

kamilrakoczy commented 2 months ago

This PR changes formal verification script to fail when it will detect any difference in expected output. It also checks if all tests present in testlist were performed.

github-actions[bot] commented 2 months ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..65316-fail-fv-on-every-difference