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chipsalliance / synlig

SystemVerilog synthesis tool
Apache License 2.0
169 stars 22 forks source link

Move yosys_mod to src directory #2557

Closed kamilrakoczy closed 2 months ago

kamilrakoczy commented 2 months ago

This PR cleans repository structure by moving yosys_mod to source directory.

github-actions[bot] commented 2 months ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..65248-move-yosys-mod-to-src-dir