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chipsalliance / synlig

SystemVerilog synthesis tool
Apache License 2.0
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mismatched input '#' expecting <EOF> error #2564

Closed gkamendje closed 2 months ago

gkamendje commented 2 months ago

I am getting the following error message while using running synthesis in ORFS. I am using the synlig binary file to read Systemverilog files. A while ago, I was able to use the synlig systemverilog plugin to read sv files in ORFS (I have tried the plugin but I get the same behaviour). 

2. Executing Verilog with UHDM frontend.
[INF:CM0023] Creating log file "/home/tmp_compile/OpenROAD-flow-scripts/flow/slpp_all/surelog.log".
[INF:PP0122] Preprocessing source file "/home/tmp_compile/OpenROAD-flow-scripts/flow/results/smic018/ltag7/base/1_synth.rtlil".
PP PREPROCESS FILE: /home/tmp_compile/OpenROAD-flow-scripts/flow/results/smic018/ltag7/base/1_synth.rtlil
[INF:PA0201] Parsing source file "/home/tmp_compile/OpenROAD-flow-scripts/flow/results/smic018/ltag7/base/1_synth.rtlil".
[SNT:PA0207] /home/tmp_compile/OpenROAD-flow-scripts/flow/results/smic018/ltag7/base/1_synth.rtlil:1: Syntax error: mismatched input '#' expecting <EOF>,
# Generated by Yosys 0.44+60 (git sha1 0fc5812dc, c++ 13.2.0-23ubuntu4 -fPIC -O3)

The pound sign # at the beginning of the .rtlil file seems to be issue. I am not sure what is going on. I do not see this behaviour in ORFS when reading Verilog files.

gkamendje commented 2 months ago

The problem was caused by the fact that the ORFS was modified to pass only the .rtlil file to the script synth.tcl during the second synthesis pass. Consequently , I had to modify my local version of synth_preamble.tcl to properly handle this case.