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chipsalliance / synlig

SystemVerilog synthesis tool
Apache License 2.0
169 stars 22 forks source link

Build(deps): Bump third_party/ibex from `87dfd07` to `2617c43` #2571

Closed dependabot[bot] closed 2 months ago

dependabot[bot] commented 2 months ago

Bumps third_party/ibex from 87dfd07 to 2617c43.

Commits
  • 2617c43 [rtl] Fix wrong address in latch RF
  • 53888bc [rtl] fix a typo.
  • 0cd7918 [doc] fix a typo.
  • 03ba286 Fix icache regression failure on VCS
  • 38c0709 [rtl] Remove ECC related data_rdata_i -> instr_X_o feedthroughs
  • 3937e48 Add SECURITY.md
  • 96a1c02 [dv] Increase iterations and instructions in riscv_rf_intg_test
  • 6ac0ddc [dv] Alter riscv_rf_intg_test to cover more scenarios
  • 9e4a950 [rtl] Fix logic for generating ECC related alerts
  • 6682336 [dv] Add spurious responses to memory agent
  • Additional commits viewable in compare view


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github-actions[bot] commented 2 months ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..dependabot/submodules/third_party/ibex-2617c43

dependabot[bot] commented 2 months ago

Superseded by #2578.