search

chipsalliance / synlig

SystemVerilog support for Yosys
Apache License 2.0
159 stars 21 forks source link

Decrease formal verification logs size #2576

Closed kamilrakoczy closed 1 week ago

kamilrakoczy commented 1 week ago

This PR decreases formal verification logs size by packing only useful logs to artifacts.

github-actions[bot] commented 1 week ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..65428-decrease-formal-verifications-logs-size