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chipsalliance / synlig

SystemVerilog synthesis tool
Apache License 2.0
169 stars 22 forks source link

Build(deps): Bump third_party/surelog from `4d8ef9e` to `01f0d2f` #2595

Closed dependabot[bot] closed 1 month ago

dependabot[bot] commented 1 month ago

Bumps third_party/surelog from 4d8ef9e to 01f0d2f.

Commits
  • 01f0d2f Merge pull request #3991 from alainmarcel/alainmarcel-patch-1
  • fbe0bdb Safer replacement of non-synth constructs
  • 6b6c364 Merge pull request #3990 from alainmarcel/alainmarcel-patch-1
  • 0d050fb More filtering for blokcing to non blocking transform
  • 2c20a5e Merge pull request #3989 from alainmarcel/blocking_to_nonblocking_ram_transform
  • f1180d9 Blocking to non-blocking RAM inference transform
  • See full diff in compare view


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github-actions[bot] commented 1 month ago

Logs difference between main branch: https://github.com/chipsalliance/synlig-logs/compare/81b61d202de48413d5f5b53c24b962001330d228..dependabot/submodules/third_party/surelog-01f0d2f

dependabot[bot] commented 1 month ago

Superseded by #2600.