casting to a vector of a given width not working properly

[jeras]

Using the git version of synlig. The sources and scripts to reproduce the problem are in the linked folder.

https://github.com/jeras/synthesis-primitives/tree/main/bugreport/yosys/techmap_ha

Seems synlig is not performing the casting of a single bit or an integer to a 16 bit vector. The issue can be seen in the generated proc.svg files.

In the single bit ena signal, the vector should be 16 bit, but is instead a single bit.

cnt <= cnt + WIDTH'(ena);

In the case of the integer 1, the vector should be 16 bit, but is instead 32 bit.

cnt <= cnt + WIDTH'(1);

Yosys built in SystemVerilog support is processing this correctly.

[tgorochowik]

Thank you for the report!

[jeras]

I did not test this yet (or checked the Verilog standard), but if there was no casting to WIDTH in the RHS, than the signal ena and the decimal constant 1 should probably be cast to the LHS width (width of cnt).