Lack of support for unions?

[Intuity]

In my SystemVerilog I have a union declared within a package - each entry of the union references a separate struct definition:

typedef union packed {
    node_raw_t raw;
    node_load_t load;
    node_signal_t signal;
    node_control_t control;
    node_control_t trace;
} node_message_t;

I'm then using this union to declare a port:

module nx_node_decoder
import NXConstants::*;
(
    // Other ports...
    , input  node_message_t               i_msg_data
    , input  logic                        i_msg_valid
    , output logic                        o_msg_ready
    // Other ports...
);

When running read_verilog_with_uhdm on this file, I get:

ERROR: hardware/rtl/node/nx_node_decoder.sv:33: Encountered unhandled type in process_port: union_var

Does this mean that union types are not supported by the UHDM plugin?

To recreate this, place the files that I have attached to the ticket into a directory and execute:

$> plugin -i uhdm
$> read_verilog_with_uhdm nx_common.svh nxconstants.sv nx_node_decoder.sv 

rtl.zip

[rkapuscik]

Thanks for your report! Indeed, although UHDM plugin supports unions, they were not handled correctly in ports. https://github.com/SymbiFlow/yosys-f4pga-plugins/pull/280 adds that support and with that the test case you linked can be parsed.

Please let us know if you run into any other errors.

[Intuity]

That works great - thanks!