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chipsalliance / tac

CHIPS Alliance Technical Advisory Council
https://www.chipsalliance.org/
Apache License 2.0
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projects: add Synlig #158

Open kgugala opened 3 months ago

kgugala commented 3 months ago

This project (source code wise) is already in CHIPS Alliance, but originally was a part of yosys-f4pga-plugins. It has later been extracted as a separate repo and renamed to Systemverilog Netlist Generator (Synlig) as the tool targets both FPGAs and ASICs. This application is formally separating it from F4PGA that is meant FPGA only.

alaindargelas commented 2 months ago

Agreed to be a added as a new project

kgugala commented 2 months ago

done - moved to data-files dir and updated to new template