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chipsalliance / tools-cocotb-verilator-build

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Differences in VCD (verilator vs icarus) #1

Closed ydnatag closed 5 years ago

ydnatag commented 5 years ago

I was testing the verilator support for cocotb using this repository and i found many differences between VCDs generated by icarus and verilator.

Test repositoy: https://github.com/andresdemski/vericocotb_test

Adder example

I found a difference in the starting value and the output is delayed one step:

As we can see in the following readable vcd, the adder.X is delayed one step (verilator output at the left).

--------------------------------------------------------------------------------------
|                                    adder.X[4:0]                                     |
--------------------------------------------------------------------------------------
| 0:00000                                  | 0:xxxxx                                  |
| 3:01111                                  | 2:01111                                  |
| 8:01001                                  | 7:01001                                  |
| 10:01111                                 | 9:01111                                  |
| 12:01011                                 | 11:01011                                 |
| 14:01101                                 | 13:01101                                 |
| 16:10100                                 | 15:10100                                 |
| 18:00110                                 | 17:00110                                 |
| 20:01110                                 | 19:01110                                 |
| 22:10001                                 | 21:10001                                 |
| 24:00101                                 | 23:00101                                 |
| 26:01111                                 | 25:01111                                 |
--------------------------------------------------------------------------------------

axi_lite_slave

Too many differences. The clk is delayed one step as it was in adder example but also there are many differences in signals like tb_axi_lite_slave.AXIML_ARREADY, tb_axi_lite_slave.AXIML_AWADDR[31:0], etc. The differences are shown here

kgugala commented 5 years ago

The differences in the initial simulation stage are caused by the fact that icarus and verilator handle the uninitialized signals differently. see: https://www.veripool.org/projects/verilator/wiki/Manual-verilator#Unknown-states

ydnatag commented 5 years ago

I suppose that but i didn't know how verilator understand uninit signals. Thanks you.

The most important difference i see is that combinational assignments are delayed and signal changes don't occur at the same time in both simulators.

ZvonimirBandic commented 5 years ago

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