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chipsalliance / tools-cocotb-verilator-build

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Differences in logging #2

Open ydnatag opened 5 years ago

ydnatag commented 5 years ago

Hi,

I updated my tools and i found differences in the logging output:

Different time step

As is shown here, the events occur at different times. Maybe the timescale 1ns/1ps is missing or not interpreted.

Error with icarus, success with veriltor

Running dff example, i get the following results:

                     | verilator                      | icarus                        
              ERRORS | 0                              | 1                             
            SIM TIME | 500.00 NS                      | 5001000000000.00 NS           
           REAL TIME | 0.35 S                         | 0.01 S                        
     SIM / REAL TIME | 1439.80 NS/S                   | 345734536080435.12 NS/S

The sim time differs and the error doesn't occurs with verilator.

axi_lite_slave sim time

axi_lite_slave example has different duration with different simulators (link): 

                     | verilator                      | icarus                        
              ERRORS | 0                              | 0                             
            SIM TIME | 1.31 NS                        | 1.26 NS                       
           REAL TIME | 0.05 S                         | 0.04 S                        
     SIM / REAL TIME | 27.24 NS/S                     | 35.84 NS/S

i'm surprised verilator has worse performance than icarus... is it right or is it just a bad performance estimation?

ZvonimirBandic commented 5 years ago

Karol, can you look into it?