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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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Integrate with FuseSoC #1

Open mithro opened 4 years ago

mithro commented 4 years ago

https://github.com/olofk/fusesoc

FuseSoC is an award-winning package manager and a set of build tools for HDL (Hardware Description Language) code.

Its main purpose is to increase reuse of IP (Intellectual Property) cores and be an aid for creating, building and simulating SoC solutions.

FuseSoC makes it easier to

  • reuse existing cores
  • create compile-time or run-time configurations
  • run regression tests against multiple simulators
  • Port designs to new targets
  • let other projects use your code
  • set up continuous integration

Would be good to have FuseSoc able to use Verible as a linter and code formatter.

mithro commented 4 years ago

FYI - @olofk @imphil @hzeller @NilsGraf

olofk commented 4 years ago

Definitely. Adding a new Edalize backend for the linter and formatter should be straightforward

fangism commented 4 years ago

FYI @msfschaffner @sjgitty Already in use? done or needs more work?

imphil commented 4 years ago

Verible lint is done in https://github.com/olofk/edalize/pull/100, verible format isn't done yet.