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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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[Feature Req] Check to detect when input or output port is not used in the design #1115

Open ghost opened 2 years ago

ghost commented 2 years ago

Summary Removing unassigned output or detecting unused input ports is an efficient and clean way to code. This could be part of lint checks.

If you can point me to a lint rule that does something similar, then I can try and contribute to this feature.

fangism commented 2 years ago

This might require more than just syntactic analysis to get correct, e.g. actual design elaboration. Most lint rules today perform only shallow syntax tree analysis. Today, the linter is limited to single-file analysis, and since you depend on module definitions (for signal direction) that could live in a different file, this falls in the domain of whole-project analysis/linting.

It might be possible to get away with a more approximate analysis using static symbol table analysis. The symbol table builder attempts to resolve symbol references to definitions and declarations.
It would just have to track usages, which would look like outbound edges.

Related #217 which needs to use the symbol table for implicit declarations, the opposite of unused signals.