Store test cases with System Verilog code in dedicated files, not as string literals in .cc file.

Verilog code samples stored in (wrapped) C string literals are far from being readable. See: https://github.com/chipsalliance/verible/blob/09c39343e7fec3508e06ee7b226156dba7c5b9e1/verilog/formatting/formatter_test.cc#L140

Store them in external files as a raw code.

Idea 1: Use .sv files with metadata embedded in comments. This would give nice syntax highlighting in editors/viewers. Example:

//# Some comment - title and description //← Comment (ignored).
//|                                      //← Empty meta line (ignored).
//| style.column_limit = 40              //← Some property (optional).
//|===================================== //← Array entry (test case) separator.
//|--- input --------------------------- //← Snippet separator with snippet name.
// verilog_syntax: parse-as-module-body  //  Every line not starting with
$foobarbaz // c1                         //  `//|` or `//#` is a part of
// c2                                    //  the snippet.
();
//|--- expected ------------------------ //← Snippet separator with snippet name.
//| eol = ""                             //← Snippet property. I guess it would
// verilog_syntax: parse-as-module-body  //  be useful to provide some way to
$foobarbaz  // c1                        //  specify custom line and file
    // c2                                //  terminators insted of explicit "\n".
    ();
//|------------------------------------- //← Explicit snippet terminator.
//|=====================================
//|--- input ---------------------------
//| s`\n`\r\n`                           //← Alternative way for snippet
// verilog_syntax: parse-as-module-body  //  customization.
$foobarbaz /* c1 */
/* c2 */
/* c3 */
();
//|--- expected ------------------------
// verilog_syntax: parse-as-module-body
$foobarbaz  /* c1 */
    /* c2 */
    /* c3 */
    ();
//|=====================================

Idea 2: Use markdown-compatible formatting. This would give possibility of highlighting multiple languages (e.g. systemverilog and json with some meta data). Or reading it like a documentation ;) Example:

> Some comment, title, description
> As a blockquote.

**config:**
~~~~~~~~~~~~~~~~~~~~~~~~~~~json
{"column_limit": 40}
~~~~~~~~~~~~~~~~~~~~~~~~~~~

****************************************

**input:**
`eol=""`
~~~~~~~~~~~~~~~~~~~~~~~~~~~systemverilog
// verilog_syntax: parse-as-module-body
$foobarbaz // c1
// c2
();
~~~~~~~~~~~~~~~~~~~~~~~~~~~

**expected:**
`s/\n$//m`
~~~~~~~~~~~~~~~~~~~~~~~~~~~systemverilog
// verilog_syntax: parse-as-module-body
$foobarbaz  // c1
    // c2
    ();
~~~~~~~~~~~~~~~~~~~~~~~~~~~

****************************************

Github-rendered example:

Some comment, title, description As a blockquote.

config:

{"column_limit": 40}

input: eol=""

// verilog_syntax: parse-as-module-body
$foobarbaz // c1
// c2
();

expected: s/\n$//m

// verilog_syntax: parse-as-module-body
$foobarbaz  // c1
    // c2
    ();

chipsalliance / verible

Store test cases with System Verilog code in dedicated files, not as string literals in .cc file. #1213