Turn off branch filtering?

[erap129]

Hello,
I am using verible-verilog-syntax to process verilog files and it is working great! I just have one question,
Sometimes my code contains looks like so:

`ifdef ABC
    ...some code...
`endif

I see that by default verible-verilog-syntax does not parse ...some_code... and it is simply removed from the syntax tree. Is there any way to turn off this feature and always process things that are in ifdef blocks?
I am using verible-verilog-syntax via the python wrapper.
Sorry if this is not a proper issue I did not find anywhere else to ask.

[karimtera]

Currently, there isn't a feature that always parse the code inside ifdef's regardless of the condition's evaluation.