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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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genvar declaration should start its own line/partition #151

Closed fangism closed 4 years ago

fangism commented 4 years ago

Input:

always_comb begin end
genvar i;
generate
for (i = 0; i < 4; i++) begin end
endgenerate

bad output:

always_comb begin
end genvar i;
generate
  for (i = 0; i < 4; i++) begin
  end
endgenerate

genvar i; should start its own partition/line.

fangism commented 4 years ago

b/148296781

fangism commented 4 years ago

Just need a case to handle kGenvarDeclaration in this switch:

https://github.com/google/verible/blob/55d88e087e4ecd40633e905f1741869325ceed76/verilog/formatting/tree_unwrapper.cc#L533