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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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~SyntaxTreeNode expensive. Use arena allocation ? #1523

Open hzeller opened 1 year ago

hzeller commented 1 year ago

When running a simple parsing (verible-verilog-syntax), the destructor of SyntaxTreeNode uses up about 15%-ish CPU. It has to destruct a vector with all their children. The whole tree is deallocated recursively, which means calling destructors of many small std::vectors.

Ideally, we shouldn't have to worry about destructing a syntax tree recursively. If we can allocate everything in an arena and deallocate at once, this would be a O(1) operation. Also, allocation would be cheaper.

Maybe std::vector can be an array (if we know the size at allocation time, this would be an excellent use of a flexible array member which would work well with arena allocation).

hzeller commented 1 year ago

In #1483 the leaf and node have been made final, so it is documented that these are the only ones interesting.

hzeller commented 1 year ago

In #1648 the SymbolPtr was moved to a single place, as preparation for some potential different way of managing instances.