chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
Other
1.35k stars 206 forks source link

Linter syntax error wrong detection #1542

Open gmlarumbe opened 1 year ago

gmlarumbe commented 1 year ago

Hi,

The verible-verilog-lint tool detects a syntax error in the wrong line (version v0.0-2492-gd122fac8).

Given the following file (test_preprocessing.sv), the error is in line 4 but it is detected in the undefined UVM macro of line 2 instead:

class test_component extends uvm_component;
    `uvm_component_utils(test_component)

    syntax_error;

    function new(string name="test_component", uvm_component parent);
        super.new(name, parent);
    endfunction : new

endclass: test_component

Running the following command:

$ ~/bin/verible-v0.0-2492-gd122fac8/bin/verible-verilog-lint test_preprocessing.sv
test_preprocessing.sv:2:5-24: preprocessing error at token "`uvm_component_utils" : Error expanding macro identifier, might not be defined before.

However, with previous version v0.0-2080-gc9674d91 the error was detected correctly:

$ ~/bin/verible-v0.0-2080-gc9674d91/bin/verible-verilog-lint test_preprocessing.sv
test_preprocessing.sv:4:17: syntax error at token ";"

Fixing the syntax error yields no output with version v0.0-2492-gd122fac8, e.g.:

class test_component extends uvm_component;
    `uvm_component_utils(test_component)

    no_syntax_error variable;

    function new(string name="test_component", uvm_component parent);
        super.new(name, parent);
    endfunction : new

endclass: test_component

Thanks!

matlupi commented 10 months ago

I did run the same example above on the revisions below and it appears it has not been fixed yet.

On v0.0-2884-g42c9491b

On v0.0-3430-g060bde0f