chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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source code indexing, symbol/fact extraction, cross-reference linking #185

Closed fangism closed 4 years ago

fangism commented 4 years ago

Gist:

Purpose:

Representation? any structure that is easily exportable/convertible to interfaces expected by other tools such as IDEs. For example https://github.com/kythe/kythe is one platform for serving source code information and metadata.

fangism commented 4 years ago

@MinaToma work is ongoing at https://github.com/MinaToma/verible

fangism commented 4 years ago

@ivan444 FYI

fangism commented 4 years ago

b/163065644

ivan444 commented 4 years ago

This is somewhat done. The indexing is working. The remaining tasks are covered with the finer grained bugs. This issue is not useful anymore.