Rejects `include inside module ports

chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

https://chipsalliance.github.io/verible/

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Closed fangism closed 4 years ago

fangism commented 4 years ago

Verible's parser currently rejects the following:

module foo(
    `include "generated_ports.svh"
);
endmodule

fangism commented 4 years ago

b/149487215