define is not properly considering

[justincdas]

Code

`include "defines.svh"

module top (
                                       clk,
                                       rst_n_sync,
                                       in,
                                       out
);

   input                                clk;
   input                    rst_n_sync;
   input                                in;
   output reg                           out;

`ifdef ASYNC_RESET_N
   always@(posedge clk or negedge rst_n_sync)begin
`else   
   always@(posedge clk)begin
`endif
     if(!rst_n_sync) begin
       out <= 1'b0;
     end else begin
`include "defines.svh"

module top (
                                       clk,
                                       rst_n_sync,
                                       in,
                                       out
);

   input                                clk;
   input                    rst_n_sync;
   input                                in;
   output reg                           out;

`ifdef ASYNC_RESET_N
   always@(posedge clk or negedge rst_n_sync)begin
`else   
   always@(posedge clk)begin
`endif
     if(!rst_n_sync) begin
       out <= 1'b0;
     end else begin
`include "defines.svh"

module top (
                                       clk,
                                       rst_n_sync,
                                       in,
                                       out
);

   input                                clk;
   input                    rst_n_sync;
   input                                in;
   output reg                           out;

`ifdef ASYNC_RESET_N
   always@(posedge clk or negedge rst_n_sync)begin
`else   
   always@(posedge clk)begin
`endif
     if(/*!rst_n*/!rst_n_sync) begin
       out <= 1'b0;
     end else begin
       out <= in;
     end
   end //always
endmodule

---

Command used verible-verilog-format --inplace temp.v

Error temp.v: temp.v:18:1-5: syntax error at token "`else" temp.v:23:10-13: syntax error at token "else" temp.v:25:6-8: syntax error at token "end"

[hzeller]

Yes, handling of preprocessing is not stellar currently and this is essentially #228 (there are other, similar issues like #241, #267). The problem you run into is that the formatter looks at the tokens as if they where in sequence without considering the branches, so sees two consecutive stars of always blocks and gets confused.

There is work in progress on this in PR #1898 - but since this project is driven by volunteers, it is moving at the pace at which there is free time.