How can I parse only verilog and not systemverilog?

chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

https://chipsalliance.github.io/verible/

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How can I parse only verilog and not systemverilog? #2048

Open arunpatro opened 10 months ago

arunpatro commented 10 months ago

Hi,

I want to restrict my application to only verilog programs and not system verilog, can you help me figure out the grammar specification for only .v files?

hzeller commented 10 months ago

Currently, we don't distinguish different dialects, so that can mean that valid Verilog programs might not be parsed correctly with Verible.

Is there a particular construct that you found Verible does not like in your Verilog files ?

It is on our TODOs since #141 - but of course that takes time. Happy to accept pull requests.