chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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Unexpected formatting of interface classes #2145

Open sriyerg opened 7 months ago

sriyerg commented 7 months ago

Test case

// Input to the formatter, preferably a reduced test case.
interface class foo;
       pure virtual function void bar(    );
  pure       virtual task baz(
  );
    endclass

Include any options or configuration used. --inplace

Actual output

// This doesn't look right.
  interface class foo; pure virtual
  function void bar()
  ; pure virtual
  task baz()
  ;
  endclass

Include any possible diagnostic messages from the formatter.

Expected or suggested output

// This result would look better from the formatter.
interface class foo;
  pure virtual function void bar();
  pure virtual task baz();
endclass

Version:

$ verible-verilog-format --version
v0.0-3617-g4f98e145
Commit  2024-03-10
Built   2024-03-11T00:27:27Z

Citations to published style guides would help. I would have expected interface classes to be formatted as a regular class, but the formatting is way off, as shown above.

sriyerg commented 7 months ago

Looks like this was already reported over 2 years ago in #1149. Nevertheless, requesting renewed attention on this, hoping not too difficult to fix. Feel free to close bug on ack.