chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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automatically comment preprocessor conditionals #2171

Open fangism opened 2 months ago

fangism commented 2 months ago

Summary

This request captures features from a script that lived outside of Verible, but some developers found useful. The script (by @jonmayergoogle ) would automatically add comments after ifdef elsif else endif directives that reflected the condition under which the section was active, and served as a readability aid.

Test cases and examples

/* Hello, world. */
alpha
`ifdef FOO
/*
beta
`ifndef BAR
*/
luke
`ifdef BUM  // is BUM defined
wookie
`endif  // this comment gets removed
r2d2
`endif
wedge

would automatically become annotated like:

/* Hello, world. */
alpha
`ifdef FOO  // FOO
/*
beta
`ifndef BAR
*/
luke
`ifdef BUM  // FOO && BUM
wookie
`endif  // FOO && BUM
r2d2
`endif  // FOO
wedge

Proposal

The implementation for this would be based on an unpreprocessed token stream. No syntactic validation is needed, as this is purely a transformation based on preprocessing tokens. The simplicity of this task means that we don't need a full syntax tree transformation/rewriting framework.

Additional context

cl/629042737 (Google)