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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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lint_tool_test: On issues, print out patch that broke. #2175

Closed hzeller closed 4 months ago

hzeller commented 4 months ago

Observed issues with recent MacOS CI.

codecov-commenter commented 4 months ago

Codecov Report

All modified and coverable lines are covered by tests :white_check_mark:

Project coverage is 92.91%. Comparing base (386f717) to head (1fd66ac). Report is 11 commits behind head on master.

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Additional details and impacted files ```diff @@ Coverage Diff @@ ## master #2175 +/- ## ========================================== - Coverage 92.91% 92.91% -0.01% ========================================== Files 359 359 Lines 26714 26712 -2 ========================================== - Hits 24821 24819 -2 Misses 1893 1893 ```

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