chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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verible-verilog-format crashing #2189

Open joaovam opened 3 weeks ago

joaovam commented 3 weeks ago

The formatter crashes with the given input: Test case

module module_0(id_491);
  output logic signed id_491; 
endmodule

Actual output

F0603 17:53:08.317050  717895 tree_unwrapper.cc:3194] Check failed: NextUnfilteredToken()->text().begin() == leaf.get().text().begin() ( vs. logic signed id_491; 
endmodule) 
*** Check failure stack trace: ***
    @     0x62913f567ec5  absl::lts_20240116::log_internal::LogMessage::PrepareToDie()
    @     0x62913f567f3d  absl::lts_20240116::log_internal::LogMessage::SendToLog()
    @     0x62913f56798f  absl::lts_20240116::log_internal::LogMessage::Flush()
    @     0x62913f56823c  absl::lts_20240116::log_internal::LogMessageFatal::~LogMessageFatal()
    @     0x62913f4080c2  verilog::formatter::TreeUnwrapper::Visit()
    @     0x62913f561f54  verible::SyntaxTreeLeaf::Accept()
    @     0x62913f463bde  verible::TreeUnwrapper::TraverseChildren()
    @     0x62913f3ffc23  verilog::formatter::TreeUnwrapper::SetIndentationsAndCreatePartitions()
    @     0x62913f3fcca3  verilog::formatter::TreeUnwrapper::Visit()
    @     0x62913f5628b0  verible::SyntaxTreeNode::Accept()
    @     0x62913f463bde  verible::TreeUnwrapper::TraverseChildren()
    @     0x62913f463f57  verible::TreeUnwrapper::VisitIndentedChildren()
    @     0x62913f464028  verible::TreeUnwrapper::VisitIndentedSection()
    @     0x62913f3fe4df  verilog::formatter::TreeUnwrapper::SetIndentationsAndCreatePartitions()
    @     0x62913f3fcca3  verilog::formatter::TreeUnwrapper::Visit()
    @     0x62913f5628b0  verible::SyntaxTreeNode::Accept()
    @     0x62913f463bde  verible::TreeUnwrapper::TraverseChildren()
    @     0x62913f463f57  verible::TreeUnwrapper::VisitIndentedChildren()
    @     0x62913f464028  verible::TreeUnwrapper::VisitIndentedSection()
    @     0x62913f3ff5f9  verilog::formatter::TreeUnwrapper::SetIndentationsAndCreatePartitions()
    @     0x62913f3fcca3  verilog::formatter::TreeUnwrapper::Visit()
    @     0x62913f5628b0  verible::SyntaxTreeNode::Accept()
    @     0x62913f463bde  verible::TreeUnwrapper::TraverseChildren()
    @     0x62913f463f57  verible::TreeUnwrapper::VisitIndentedChildren()
    @     0x62913f464028  verible::TreeUnwrapper::VisitIndentedSection()
    @     0x62913f3fe504  verilog::formatter::TreeUnwrapper::SetIndentationsAndCreatePartitions()
    @     0x62913f3fcca3  verilog::formatter::TreeUnwrapper::Visit()
    @     0x62913f5628b0  verible::SyntaxTreeNode::Accept()
    @     0x62913f463bde  verible::TreeUnwrapper::TraverseChildren()
    @     0x62913f408e9e  verilog::formatter::TreeUnwrapper::VisitNewUnwrappedLine()
    @     0x62913f3fdfc8  verilog::formatter::TreeUnwrapper::SetIndentationsAndCreatePartitions()
    @     0x62913f3fcca3  verilog::formatter::TreeUnwrapper::Visit()
    @     0x62913f5628b0  verible::SyntaxTreeNode::Accept()
    @     0x62913f462799  verible::TreeUnwrapper::Unwrap()
    @     0x62913f3ad8bd  verilog::formatter::Formatter::Format()
    @     0x62913f3aac6f  verilog::formatter::FormatVerilog()
    @     0x62913f3ab03b  verilog::formatter::FormatVerilog()
    @     0x62913f38af1c  formatOneFile()
    @     0x62913f38b863  main
    @     0x743a54a29d90  (unknown)
*** SIGABRT received at time=1717447988 on cpu 22 ***
PC: @     0x743a54a969fc  (unknown)  pthread_kill
    @     0x62913f396e9b         64  absl::lts_20240116::WriteFailureInfo()
    @     0x62913f3970b0         96  absl::lts_20240116::AbslFailureSignalHandler()
    @     0x743a54a42520  (unknown)  (unknown)
Aborted

The code seems valid so it should be accepted and formatted accordingly.