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chipsalliance
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verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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Use Windows CI runner 2019 (2022 has issues).
#2194
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hzeller
closed
3 months ago
hzeller
commented
3 months ago
Issues #2193
Issues #2193