chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
Other
1.25k stars 195 forks source link

Dynamic code with macros is not parsed properly #2197

Open bhappel-ciena opened 2 weeks ago

bhappel-ciena commented 2 weeks ago

Describe the bug

Code that is dynamically generated with IF ELSE macros at compile time does not get parsed properly.

To Reproduce

// Input to the formatter, preferably a reduced test case.
`ifdef OPTION
option_module #() u_my_module (
`else
default_module #() u_my_module (
`endif
    .my_signal(),
    .more_signals()
);

Include any options used.

Actual behavior:

Did it reject valid code? or crash?

This code is rejected as a syntax error

Expected behavior

I would expect code that compiles to be able to be parsed without throwing a syntax error.