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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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invalid memory access in tree_unwrapper.cc (kConditionalStatement) #220

Closed fangism closed 4 years ago

fangism commented 4 years ago

The logic in the handling of else-if partitions is buggy.

This test case:

function foo;if (zz) return 0;else if (yy) return 1;endfunction

is triggering AddressSanitizer bugs here:

https://github.com/google/verible/blob/64a4e8f0a448a93ee845442ff7074402820fac08/verilog/formatting/tree_unwrapper.cc#L1070

When the token range is empty(), which happens during the ApplyPreOrder traversal.

I'll take this one.

fangism commented 4 years ago

b/150183144