chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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clang-tidy-cached: don't output progress updates if not isatty() #2200

Closed hzeller closed 3 months ago

hzeller commented 3 months ago

.. it resutlts in noisy output in the CI.