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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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Add a regex configration for the signal name style rule #2204

Open sconwayaus opened 1 week ago

sconwayaus commented 1 week ago

Adding regex configuration to the signal name style rule, part of issue #2074 .

codecov-commenter commented 1 week ago

Codecov Report

All modified and coverable lines are covered by tests :white_check_mark:

Project coverage is 92.92%. Comparing base (054f273) to head (56359eb). Report is 14 commits behind head on master.

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Additional details and impacted files ```diff @@ Coverage Diff @@ ## master #2204 +/- ## ========================================== - Coverage 92.92% 92.92% -0.01% ========================================== Files 359 359 Lines 26740 26768 +28 ========================================== + Hits 24848 24874 +26 - Misses 1892 1894 +2 ```

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sconwayaus commented 2 days ago

Are you still working it it ? (as it is marked as draft) I was. Did some real world testing with it during the week but I think this is ready to move forward.