Open benjamin051000 opened 1 month ago
I think that was mostly a request by DV engineers that like to inject better ways to get test vector, though it would probably good to have that as an explicit style guide somewhere so that it is easy to refer to.
Maybe @fangism remembers the details ?
$random breaks reproducibility:
Quote from the style guide: "$random and $dist_*: these functions should not be used as they are not part of the SystemVerilog random stability model and may break simulation reproducibility. Use $urandom or randomize() instead."
invalid-system-task-function
states:When I use
$random
in a SystemVerilog file, Verible prints this warning:I'm curious as to why it's discouraged to use
$random
and instead use$urandom
. Forgive me, I'm pretty new to verilog & systemverilog. Thanks for the clarification!