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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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New lint rule for checking labels of generate blocks #311

Closed msfschaffner closed 4 years ago

msfschaffner commented 4 years ago

Some style guides recommend prefixing all generate block labels in a design with an identifier like g_* or gen_*. Hence, a Verible lint rule that can check for such patterns in generate labels would be useful.

if (ParamXY) begin : gen_xy
    ...
end
msfschaffner commented 4 years ago

b/157748205