chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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[online demo] deploy to edaplayground.com or our own playground? #340

Open fangism opened 4 years ago

fangism commented 4 years ago

To raise-awareness and lower the barrier to testing Verible, should we push to deploy at edaplayground.com or consider our own playground? @mithro WDYT?

When we were brainstorming project ideas, here are some of the ideas we had for tools/panels in the interface:

svenka3 commented 3 years ago

I would be thrilled to see an online Verible on its own site (without other commercial simulators, that complicates some end-users' use cases - I personally have heard many users saying that). On what else to add to such interface - how about a document generator (especially for SV/UVM) - similar to Doxygen/NaturalDocs. And a way to export/download formatted code (Consider user has code that's unformatted, uses this site to format, then pull the formatted code back to his/her use).

Thanks Srini

mithro commented 3 years ago

On the topic of documentation (which is mostly unrelated to verible), we are currently using Sphinx for documenting our Verilog projects (which is very popular in the Python community). The sphinx-verilog-domain module adds Verilog / SystemVerilog support and it goes well with the sphinxcontrib-hdl-diagrams module for generating cool RTL diagrams automagically, Symbolator for generating module diagrams and sphinxcontrib-wavedrom for creating nice waveform diagrams.

fangism commented 3 years ago

Nevertheless, comment-based documentation extraction is a very reasonable feature set to ask for, do file a separate issue for that. It could be further enhanced by our ongoing search index extraction project using Kythe as well.