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chipsalliance / verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
https://chipsalliance.github.io/verible/
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Kythe: add verification tests to Verible's CI #395

Closed ivan444 closed 4 years ago

ivan444 commented 4 years ago

Prevent breakages of Kythe extraction logic by running the verification tests as a part of Verible's continuous integration.

The initial set of Kythe verification tests is being added with PR #386.

Umbrella issue: #185

MinaToma commented 4 years ago

Re-opening because the tests aren't added to the CI yet.

fangism commented 4 years ago

co-assigning to @ivan444 to help with the starlark test rules.